Examples of a device isolation method for a semiconductor device include a local oxidation of silicon (LOCOS) method and a trench isolation method. The LOCOS method may be employed by electrically isolating devices using selective oxidation. The trench isolation method may be employed by electrically isolating devices using trenches.
The LOCOS method has been used in the manufacture of semiconductor devices. In the LOCOS method, a thermal oxidation process is performed on a partially exposed semiconductor substrate to form a field oxide layer. Although the LOCOS method may be uncomplicated to implement, there can be several drawbacks of the LOCOS method. For example, using the LOCOS method, a punch-through may occur because of, for example, either a bird's beak or a thin field oxide layer. In addition, when the semiconductor device is highly integrated, the width of the device isolation region may be reduced and consequently, it may be difficult to isolate the devices using the LOCOS method.
The trench isolation method is designed to overcome at least some of the drawbacks of the LOCOS method. The trench isolation method can include forming trenches in a semiconductor substrate and performing a chemical vapor deposition (CVD) process to fill the trenches with an insulating material. Compared to the LOCOS method, the trench isolation method may provide an effective device isolation depth for an isolation region with the same width. However, using the trench isolation method, the width of the device isolation region (i.e., the width of a trench) may be reduced due to the high integration of semiconductor devices. Thus, it may be more difficult to fill the device isolation region with an insulating material.
FIGS. 1A through 1E present sectional views illustrating a conventional method of forming a trench in a semiconductor substrate.
Referring to FIG. 1A, a pad oxide layer 20, a nitride layer 30, and an anti-reflective layer 40 are formed on the semiconductor substrate 10. A photoresist pattern 60 is formed above the anti-reflective layer 40 to define a trench region.
Referring to FIG. 1B, an etching process is performed on the structure in FIG. 1A to form an anti-reflective layer pattern 40p, a nitride layer pattern 30p and a pad oxide layer pattern 20p and to further expose a portion of the semiconductor substrate 10. A polymer P layer may be formed on the sidewalls of the nitride layer pattern 30p and the pad oxide layer pattern 20p. 
Referring to FIGS. 1C and 1D, an etching process is performed again on the structure in FIG. 1B to form a trench 70. When the etching process is performed the second time, the polymer P may serve as an etch mask. After the etching process, an ashing process is performed to remove the photoresist pattern 60 and the polymer P. After the polymer P is removed, a ledge A may be formed at a rounded top edge of the trench 70 as illustrated in FIG. 1D.
If over-etching occurs on the nitride layer pattern 30p and the pad oxide layer pattern 20p, the ledge A may be formed at a lower position as illustrated in FIG. 1E.
If the side surfaces of the trench 70 are uneven (i.e., if the side surfaces have an uneven slope) as illustrated in FIGS. 1D and 1E, the trench 70 may be partially filled at most with an insulating material. For example, when the trench 70 is filled with an insulating material, voids can be generated in a center portion of the trench 70 because, at least in part, of abnormal deposition of an insulating layer on the ledge A. This phenomenon may occur more frequently when the integration degree of a semiconductor device increases and/or the trench width decreases.